Existing complex programmable logic devices (CPLD), field programmable gate array (FPGA), and application specific integrated circuit (ASIC) technologies do not directly support implementation of internal bidirectional signals without the use of a dedicated direction control signal. Current architectures allow for I/O pins to be configured as bidirectional signals. However, these architectures do not allow for two of these pins to be directly tied together while maintaining a truly asynchronous bidirectional data path. The only existing solution to this unique problem is the introduction of a data direction control signal, which makes asynchronous bidirectional communication impossible.
A common method of implementing an asynchronous bidirectional half duplex communications link is the use of an open drain or open collector driver and a logic receiver at each end of the communications link which has a pull up resistor to a common voltage. It is possible for multiple devices to be connected to the same link. In the case of multiple devices on the same link, when one device talks, all other devices on the net receive the message. In this case, an agreed means of addressing is used so that an intended recipient knows the message is for him. At times it is desirable or necessary to isolate certain devices on such a link. This can arise because multiple devices may share the same address or there may not be enough addresses to accommodate the number of devices. Alternately it may be desirable to isolate a failing device from the link so that the failing device does not render the link inoperative. Many other instances arise where it is desirable to be able to inexpensively route and manipulate such communications links. Typically open drain and open collector communication links can be isolated, switched and routed using analog switches. Analog switches are large and expensive and this limits the complexity of the switching which can be easily achieved. Therefore, it is desirable to be able to switch and route such signals using logic gates which could reside on a CPLD, FPGA, ASIC or other highly integrated, inexpensive device.
As a further issue, a bidirectional data communication bus implemented on a single transmission line typically has a limited data communication range due to intrinsic capacitance established in the transmission line as the length increases. For example, Inter-Integrated Circuit (I2C) communication is one example of a bidirectional data communication bus protocol for half duplex open collector communications. The protocol defines the maximum bus capacitive load to be 400 pF and the maximum rise time for the data signal to be 1 μs for I2C communications. This implies that the I2C bus cannot traverse great lengths without violating the specification. A rule of thumb used by many system designers is to maintain I2C bus lengths less than one meter. Therefore, a need exists in the art for an approach to extending range of a bidirectional data communication bus, such as a half duplex open collector communications bus implemented via a single data transmission line.